Impedance modeling and analysis of multi-stacked on-chip power distribution network in 3D ICs

An accurate impedance modeling of a multi-stacked on-chip power distributed network (PDN) based on through-silicon-vias (TSVs) is vitally important to estimate the electrical performance in three-dimensional integrated circuits (3D ICs). This paper proposes method for calculating matrix PDN, which mainly consists arbitrarily TSVs and grid-type PDNs. First, real stack-up structure PDN separated into discrete components intentionally. Then, equivalent lumped circuit models all are assembled whole build transmission through relationship between nodal voltage current. Finally, can be derived matrix. In this paper, coupling distributional effect considered (TMM). The proposed replaces simulation complex model with calculation. verification results show that deviation resonant frequency about 6 $$\%$$ conversation time 99.9 compared HFSS model. It accurately quickly calculate PDN.